The present invention relates generally to the generation and checking of redundancy data.
In conventional mass data storage systems employing a group of storage devices, it is known to use error correction methodologies to correct or to regenerate data for a particular failed storage device by use of a redundancy code which is generated and stored on other storage devices. These conventional correction methodologies require that all the relevant data be combined in a memory before it can be processed to generate or to regenerate a code word. As used herein, the term xe2x80x9ccode wordxe2x80x9d refers to a group of bytes of data and the redundancy code generated from such group.
The present invention is a method and apparatus for dynamic alignment of a group of associated portions of a code word for presentation to a processing circuit. In a preferred embodiment, the invention sequences in alignment a group of associated code word portions which are each stored independently of one another and which will be processed together to either generate the redundancy for a code word or correct a faulty associated portion of a code word by use of the redundant data.
A preferred embodiment of the present invention is directed to a system for synchronizing parallel processing, by an array correction circuit, of a group of blocks of data transferred over parallel buses between two groups of storage devices.
The preferred embodiment includes two circuits, each one associated with one of the two groups of storage devices, for asserting a ready signal from each of the storage devices. These ready signals are independently asserted, with each ready signal being asserted when its associated storage device is ready to be accessed. This access may be a read or a write of a preselected number of bytes of data, generally a block of data. The array correction circuit provides enable signals to the storage devices when all the necessary ready signals are received. Ready signals from both groups are needed since the data must be read from one group and stored in the other group (after processing). In one embodiment, the storage devices are buffer memories in a data path from an external computer to a group of disk drives. One group of buffers is connected to the disk drives and the other groups is connected to the external computer.
Two mask registers are provided, one for each group of storage devices. Each mask register can be programmed to select a set of the storage devices in a group. Each mask register generates a master ready signal when all the read signals of the selected set are present.
The array correction circuit includes a sequencer and a counter. The sequencer is responsive to the concurrent assertion of the master ready signals of the two mask register circuits to enable, with strobe signals, the transfer of a block of data from storage devices which are to be read and process them together. After processing, the blocks of data are loaded into the storage devices which are to be written in response to strobe signals asserted by the sequencer. The counter permits the array correction circuit to establish when an entire block has been read from each Of the storage devices by sequencing through a count equal to the block size. Processing of code words of the remaining plurality of blocks of data will be inhibited until both the master ready signals are again asserted concurrently.
Data is properly synchronized between the selected groups of storage devices and the array correction circuit by use of the present invention in an efficient and convenient manner.